View AMP04EP_8866235.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a amp04* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram 2 3 8 1 6 5 in(? in(+) input buffers r gain 100k ref 100k v out 11k 11k features single supply operation low supply current: 700 m a max wide gain range: 1 to 1000 low offset voltage: 150 m v max zero-in/zero-out single-resistor gain set 8-pin mini-dip and so packages applications strain gages thermocouples rtds battery powered equipment medical instrumentation data acquisition systems pc based instruments portable instrumentation precision single supply instrumentation amplifier general description the amp04 is a single-supply instrumentation amplifier designed to work over a +5 volt to 15 volt supply range. it offers an excellent combination of accuracy, low power con- sumption, wide input voltage range, and excellent gain performance. gain is set by a single external resistor and can be from 1 to 1000. input common-mode voltage range allows the amp04 to handle signals with full accuracy from ground to within 1 volt of the positive supply. and the output can swing to within 1 volt of the positive supply. gain bandwidth is over 700 khz. in addi- tion to being easy to use, the amp04 draws only 700 m a of sup- ply current. for high resolution data acquisition systems, laser trimming of low drift thin-film resistors limits the input offset voltage to under 150 m v, and allows the amp04 to offer gain nonlinearity of 0.005% and a gain tempco of 30 ppm/ c. a proprietary input structure limits input offset currents to less than 5 na with drift of only 8 pa/ c, allowing direct connection of the amp04 to high impedance transducers and other signal sources. * protected by u.s. patent no. 5,075,633. the amp04 is specified over the extended industrial (C40 c to +85 c) temperature range. amp04s are available in plastic and ceramic dip plus so-8 surface mount packages. contact your local sales office for mil-std-883 data sheet and availability. pin connections 8-lead epoxy dip (p suffix) 8-lead narrow-body so (s suffix) 1 2 3 4 8 7 6 5 amp-04 r gain v+ v out ref r gain ?n +in v amp-04 v+ r gain v out ref r gain ?n +in v
amp04Cspecifications electrical characteristics amp04e amp04f parameter symbol conditions min typ max min typ max units offset voltage input offset voltage v ios 30 150 300 m v C40 c t a +85 c 300 600 m v input offset voltage drift tcv ios 36 m v/ c output offset voltage v oos 0.5 1.5 3 mv C40 c t a +85 c3 6mv output offset voltage drift tcvoos 30 50 m v/ c input current input bias current i b 22 30 40 na C40 c t a +85 c50 60na input bias current drift tci b 65 65 pa/ c input offset current i os 15 10na C40 c t a +85 c10 15na input offset current drift tci os 8 8 pa/ c input common-mode input resistance 4 4 g w differential input resistance 4 4 g w input voltage range v in 0 3.0 0 3.0 v common-mode rejection cmr 0 v v cm 3.0 v g = 1 60 80 55 db g = 10 80 100 75 db g = 100 90 105 80 db g = 1000 90 105 80 db common-mode rejection cmr 0 v v cm 2.5 v C40 c t a +85 c g = 1 55 50 db g = 10 75 70 db g = 100 85 75 db g = 1000 85 75 db power supply rejection psrr 4.0 v v s 12 v C40 c t a +85 c g = 1 95 85 db g = 10 105 95 db g = 100 105 95 db g = 1000 105 95 db gain (g = 100 k/r gain ) gain equation accuracy g = 1 to 100 0.2 0.5 0.75 % g = 1 to 100 C40 c t a +85 c 0.8 1.0 % g = 1000 0.4 0.75 % gain range g 1 1000 1 1000 v/v nonlinearity g = 1, r l = 5 k w 0.005 % g = 10, r l = 5 k w 0.015 % g = 100, r l = 5 k w 0.025 % gain temperature coefficient d g/ d t 30 50 ppm/ c output output voltage swing high v oh r l = 2 k w 4.0 4.2 4.0 v r l = 2 k w C40 c t a +85 c 3.8 3.8 v output voltage swing low v ol r l = 2 k w C40 c t a +85 c 2.0 2.5 mv output current limit sink 30 30 ma source 15 15 ma rev. a C2C (v s = +5 v, v cm = +2.5 v, t a = +25 8 c unless otherwise noted)
amp04 rev. a C3C amp04e amp04f parameter symbol conditions min typ max min typ max units noise noise voltage density, rti e n f = 1 khz, g = 1 270 270 nv/ ? hz f = 1 khz, g = 10 45 45 nv/ ? hz f = 100 hz, g = 100 30 30 nv/ ? hz f = 100 hz, g = 1000 25 25 nv/ ? hz noise current density, rti i n f = 100 hz, g = 100 4 4 pa/ ? hz input noise voltage e n p-p 0.1 to 10 hz, g = 1 7 7 m v p-p 0.1 to 10 hz, g = 10 1.5 1.5 m v p-p 0.1 to 10 hz, g = 100 0.7 0.7 m v p-p dynamic response small signal bandwidth bw g = 1, C3 db 300 300 khz power supply supply current i sy 550 700 700 m a C40 c t a +85 c 850 850 m a specifications subject to change without notice. electrical characteristics amp04e amp04f parameter symbol conditions min typ max min typ max units offset voltage input offset voltage v ios 80 400 600 m v C40 c t a +85 c 600 900 m v input offset voltage drift tcv ios 36 m v/ c output offset voltage v oos 13 6 mv C40 c t a +85 c6 9mv output offset voltage drift tcvoos 30 50 m v/ c input current input bias current i b 17 30 40 na C40 c t a +85 c50 60na input bias current drift tci b 65 65 pa/ c input offset current i os 25 10na C40 c t a +85 c15 20na input offset current drift tci os 28 28 pa/ c input common-mode input resistance 4 4 g w differential input resistance 4 4 g w input voltage range v in C12 +12 C12 +12 v common-mode rejection cmr C12 v v cm +12 v g = 1 60 80 55 db g = 10 80 100 75 db g = 100 90 105 80 db g = 1000 90 105 80 db common-mode rejection cmr C11 v v cm +11 v C40 c t a +85 c g = 1 55 50 db g = 10 75 70 db g = 100 85 75 db g = 1000 85 75 db power supply rejection psrr 2.5 v v s 18 v C40 c t a +85 c g = 1 75 70 db g = 10 90 80 db g = 100 95 85 db g = 1000 95 85 db (v s = 6 5 v, v cm = 0 v, t a = +25 8 c unless otherwise noted)
amp04 rev. a C4C amp04e amp04f parameter symbol conditions min typ max min typ max units gain (g = 100 k/r gain ) gain equation accuracy g = 1 to 100 0.2 0.5 0.75 % g = 1000 0.4 0.75 % g = 1 to 100 C40 c t a +85 c 0.8 1.0 % gain range g 1 1000 1 1000 v/v nonlinearity g = 1, r l = 5 k w 0.005 0.005 % g = 10, r l = 5 k w 0.015 0.015 % g = 100, r l = 5 k w 0.025 0.025 % gain temperature coefficient d g/ d t 30 50 ppm/ c output output voltage swing high v oh r l = 2 k w +13 +13.4 +13 v r l = 2 k w C40 c t a +85 c +12.5 +12.5 v output voltage swing low v ol r l = 2 k w C40 c t a +85 c C14.5 C14.5 v output current limit sink 30 30 ma source 15 15 ma noise noise voltage density, rti e n f = 1 khz, g = 1 270 270 nv/ ? hz f = 1 khz, g = 10 45 45 nv/ ? hz f = 100 hz, g = 100 30 30 nv/ ? hz f = 100 hz, g = 1000 25 25 nv/ ? hz noise current density, rti i n f = 100 hz, g = 100 4 4 pa/ ? hz input noise voltage e n p-p 0.1 to 10 hz, g = 1 5 5 m v p-p 0.1 to 10 hz, g = 10 1 1 m v p-p 0.1 to 10 hz, g = 100 0.5 0.5 m v p-p dynamic response small signal bandwidth bw g = 1, C3 db 700 700 khz power supply supply current i sy 750 900 900 m a C40 c t a +85 c 1100 1100 m a specifications subject to change without notice. wafer test limits parameter symbol conditions limit units offset voltage input offset voltage v ios 300 m v max output offset voltage v oos 3 mv max input current input bias current i b 40 na max input offset current i os 10 na max input common-mode rejection cmr 0 v v cm 3.0 v g = 1 55 db min g = 10 75 db min g = 100 80 db min g = 1000 80 db min common-mode rejection cmr v s = 15 v, C12 v v cm +12 v g = 1 55 db min g = 10 75 db min g = 100 80 db min (v s = +5 v, v cm = +2.5 v, t a = +25 8 c unless otherwise noted)
amp04 rev. a C5C parameter symbol conditions limit units g = 1000 80 db min power supply rejection psrr 4.0 v v s 12 v g = 1 85 db min g = 10 95 db min g = 100 95 db min g = 1000 95 db min gain (g = 100 k/r gain ) gain equation accuracy g = 1 to 100 0.75 % max output output voltage swing high v oh r l = 2 k w 4.0 v min output voltage swing low v ol r l = 2 k w 2.5 mv max power supply supply current i sy v s = 15 900 m a max 700 m a max note electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v common-mode input voltage 2 . . . . . . . . . . . . . . . . . . 18 v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . 36 v output short-circuit duration to gnd . . . . . . . . . . indefinite storage temperature range z package . . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +175 c p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range amp04a . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c amp04e, f . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature range z package . . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +175 c p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c package type q ja 3 q jc units 8-pin cerdip (z) 148 16 c/w 8-pin plastic dip (p) 103 43 c/w 8-pin soic (s) 158 43 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. 3 q ja is s pecified for the worst case conditions, i.e., q ja is specified for device in socket for cerdip, p-dip, and lcc packages; q ja is specified for device soldered in circuit board for soic package. ordering guide temperature v os @ +5 v package package model range t a = +25 8 c description option AMP04EP xind 150 m v plastic dip n-8 amp04es xind 150 m v soic so-8 amp04fp xind 300 m v plastic dip n-8 amp04fs xind 300 m v soic so-8 amp04fs-reel xind 150 m v soic so-8 amp04fs-reel7 xind 150 m v soic so-8 amp04gbc +25 c 300 m v dice characteristics amp04 die size 0.075 0.99 inch, 7,425 sq. mils. substrate (die backside) is connected to v+. transistor count, 81.
amp04 rev. a C6C applications common-mode rejection the purpose of the instrumentation amplifier is to amplify the difference between the two input signals while ignoring offset and noise voltages common to both inputs. one way of judging the devices ability to reject this offset is the common-mode gain, which is the ratio between a change in the common-mode voltage and the resulting output voltage change. instrumenta- tion amplifiers are often judged by the common-mode rejection ratio, which is equal to 20 log 10 of the ratio of the u ser-selected differe ntial signal gain to the common-mode gain, commonly called the cmrr. the amp04 offers excellent cmrr, guaran- teed to be greater than 90 db at gains of 100 or greater. input offsets attain very low temperature drift by proprietary laser- trimmed thin-film resistors and high gain amplifiers. input common-mode range includes ground the amp04 employs a patented topology (figure 1) that uniquely allows the common-mode input voltage to truly extend to zero volts where other instrumentation amplifiers fail. to il- lustrate, take for example the single supply, gain of 100 instru- mentation amplifier as in figure 2. as the inputs approach zero volts, in order for the output to go positive, amplifier as output (v oa ) must be allowed to go below ground, to C0.094 volts. clearly this is not possible in a single supply environment. con- sequently this instrumentation amplifier configurations input common-mode voltage cannot go below about 0.4 volts. in comparison, the amp04 has no such restriction. its inputs will function with a zero-volt common-mode voltage. 2 3 8 1 6 5 in(? in(+) input buffers r gain 100k ref 100k v out 11k 11k figure 1. functional block diagram b a v oa 100k 20k 20k 100k 2127 w 0v v out 0v 0.01v 0.01v + 4.7 m a 5.2 m a 4.7 m a v ob ?094v v in figure 2. gain = 100 instrumentation amplifier input common-mode voltage below ground although not tested and guaranteed, the amp04 inputs are bi- ased in a way that they can amplify signals linearly with com mon- mode voltage as low as C0.25 volts below ground. this holds true over the industrial temperature range from C40 c to +85 c. extended positive common-mode range on the high side, other instrumentation amplifier configura- tions, such as the three op amp instrumentation amplifier, can have severe positive common-mode range limitations. figure 3 shows an example of a gain of 1001 amplifier, with an input common-mode voltage of 10 volts. for this circuit to function, v ob must swing to 15.01 volts in order for the output to go to 10.01 volts. clearly no op amp can handle this swing range (given a +15 v supply) as the output will saturate long before it reaches the supply rails. again the amp04s topology does not have this limitation. figure 4 illustrates the amp04 operating at the same common-mode conditions as in figure 3. none of the internal nodes has a signal high enough to cause amplifier satu- ration. as a result, the amp04 can accommodate much wider common-mode range than most instrumentation amplifiers. b v oa 100k 100k a v ob r r r +5v +15.01v r 10.01 +10.00v +10.01v 200 w 50 m a figure 3. gain = 1001, three op amp instrumentation amplifier +10.00v +10.01v 100k 100k v out 11k ?5v +10.01v 100 w 100 m a +15v 11k +11.111v + 0.1 m a 100.1 m a ?5v +15v +10v figure 4. gain = 1000, amp04
amp04 rev. a C7C programming the gain the gain of the amp04 is programmed by the user by selecting a single external resistorr gain : gain = 100 k w / r gain the output voltage is then defined as the differential input volt- age times the gain. v out = ( v in + C v in C ) gain in single supply systems, offsetting the ground is often desired for several reasons. ground may be offset from zero to provide a quieter signal reference point, or to offset zero to allow a unipolar signal range to represent both positive and negative values. in noisy environments such as those having digital switching, switching power supplies or externally generated noise, ground may not be the ideal place to reference a signal in a high accu- racy system. often, real world signals such as temperature or pressure may generate voltages that are represented by changes in polarity. in a single supply system the signal input cannot be allowed to go below gr ound, and therefore the signal must be offset to accom- modate this change in polarity. on the amp04, a reference in- put pin is provided to allow offsetting of the input range. the gain equation is more accurately represented by including this reference input. v out = ( v in + C v in C ) gain + v ref grounding the most common problems encountered in high performance analog instrumentation and data acquisition system designs are found in the management of offset errors and ground noise. primarily, the designer must consider temperature differentials and thermocouple effects due to dissimilar metals, ir voltage drops, and the effects of stray capacitance. the problem is greatly compounded when high speed digital circuitry, such as that accompanying data conversion components, is brought into the proximity of the analog section. considerable noise and error contributions such as fast-moving logic signals that easily propagate into sensitive analog lines, and the unavoidable n oise common to digital supply lines must all be dealt with if the accu- racy of the carefully designed analog section is to be preserved. besides the temperature drift errors encountered in the ampli- fier, thermal errors due to the supporting discrete components should be evaluated. the use of high quality, low-tc compo- nents where appropriate is encouraged. what is more impo rtant, large thermal gradients can create not only unexpected changes in component values, but also generate significant thermoelec- tric voltages due to the interface between dissimilar metals such as lead solder, copper wire, gold socket contacts, kovar lead frames, etc. thermocouple voltages developed at these junc- tions commonly exceed the tcv os contribution of the amp04. component layout that takes into account the power dissipation at critical locations in the circuit and minimizes gra- dient effects and differential common-mode voltages by taking advantage of input symmetry will minimize many of these errors. high accuracy circuitry can experience considerable error con- tributions due to the coupling of stray voltages into sensitive areas, including high impedance amplifier inputs which benefit from such techniques as ground planes, guard rings, and shields. careful circuit layout, including good grounding and signal routing practice to minimize stray coupling and ground loops is recommended. leakage currents can be minimized by using high quality socket and circuit board materials, and by carefully cleaning and coating complete board assemblies. as mentioned above, the high speed transition noise found in logic circuitry is the sworn enemy of the analog circuit designer. great care must be taken to maintain separation between them to minimize coupling. a major path for these error voltages will be found in the power supply lines. low impedance, load re- lated variations and noise levels that are completely acceptable in the high thresholds of the digital domain make the digital supply unusable in nearly all high performance analog applica- tions. the user is encouraged to maintain separate power and ground between the analog and digital systems wherever pos- sible, joining only at the supply itself if necessary, and to ob- serve careful grounding layout and bypass capacitor scheduling in sensitive areas. input shield drivers high impedance sources and long cable runs from remote trans- ducers in noisy industrial environments commonly experience significant amounts of noise coupled to the inputs. both stray capacitance errors and noise coupling from external sources can be minimized by running the input signal through shielded cable. the cable shield is often grounded at the analog input common, however improved dynamic noise rejection and a re- duction in effective cable capacitance is achieved by driving the shield with a buffer amplifier at a potential equal to the voltage seen at the input. driven shields are easily realized with the amp04. examination of the simplified schematic shows that the potentials at the gain set resistor pins of the amp04 follow the inputs precisely. as shown in figure 5, shield drivers are easily realized by buffering the potential at these pins by a dual, single supply op amp such as the op213. alternatively, applications with single-ended sources or that use twisted-pair cable could drive a single shield. to minimize error contributions due to this additional circuitry, all components and wiring should re- main in proximity to the amp04 and careful grounding and by- passing techniques should be observed. 2 3 8 1 6 v out 1/2 op-213 1/2 op-213 figure 5. cable shield drivers
amp04 rev. a C8C compensating for input and output errors to achieve optimal performance, the user needs to take into account a number of error sources found in instrumentation amplifiers. these consist primarily of input and output offset voltages and leakage currents. the input and output offset voltages are independent from one another, and must be considered separately. the input offset component will of course be directly multiplied by the gain of the amplifier, in contrast to the output offset voltage that is in- dependent of gain. therefore, the output error is the dominant factor at low gains, and the input error grows to become the greater problem as gain is increased. the overall equation for offset voltage error referred to the output (rto) is: v os ( rto ) = ( v ios g ) + v oos where v ios is the input offset voltage and v oos the output offset voltage, and g is the programmed amplifier gain. the change in these error voltages with temperature must also be taken into account. the specification tcv os , referred to the output, is a combination of the input and output drift specifica- tions. again, the gain influences the input error but not the out- put, and the equation is: tcv os ( rto ) = (tcv ios g) + tcv oos in some applications the user may wish to define the error con- tribution as referred to the input, and treat it as an input error. the relationship is: tcv os ( rti ) = tcv io s + ( tcv oos / g ) the bias and offset currents of the input transistors also have an impact on the overall accuracy of the input signal. the input leakage, or bias currents of both inputs will generate an addi- tional offset voltage when flowing through the signal source re- sistance. changes in this error component due to variations with signal voltage and temperature can be minimized if both input source resistances are equal, reducing the error to a common- mode voltage which can be rejected. the difference in bias cur- rent between the inputs, the offset current, generates a differen- tial error voltage across the source resistance that should be taken into account in the users design. in applications utilizing floating sources such as thermocouples, transformers, and some photo detectors, the user must take care to provide some current path between the high impedance in- puts and analog ground. the input bias currents of the amp04, although extremely low, will charge the stray capacitance found in nearby circuit traces, cables, etc., and cause the input to drift erratically or to saturate unless given a bleed path to the analog common. again, the use of equal resistance values will create a common input error voltage that is rejected by the amplifier. reference input the v ref input is used to set the system ground. for dual sup- ply operation it can be connected to ground to give zero volts out with zero volts differential input. in single supply systems it could be connected either to the negative supply or to a pseudo- ground between the supplies. in any case, the ref input must be driven with low impedance. noise filtering unlike most previous instrumentation amplifiers, the output stages inverting input (pin 8) is accessible. by placing a capaci- tor across the amp04s feedback path (figure 6, pins 6 and 8) 2 3 8 1 6 5 in(? in(+) input buffers r gain 100k ref 100k v out 11k 11k r gain c ext lp = 1 2 p (100k) c ext figure 6. noise band limiting a single-pole low-pass filter is produced. the cutoff frequency (f lp ) follows the relationship: f lp = 1 2 p (100 k w ) c ext filtering can be applied to reduce wide band noise. figure 7a shows a 10 hz low-pass filter, gain of 1000 for the amp04. fig- ures 7b and 7c illustrate the effect of filtering on noise. the photo in figure 7b shows the output noise before filtering. by adding a 0.15 m f capacitor, the noise is reduced by about a factor of 4 as shown in figure 7c. 7 1 6 5 4 3 2 8 +15v ?5v 100 0.15 m f figure 7a. 10 hz low-pass filter 10 90 100 0% 5mv 10ms figure 7b. unfiltered amp04 output
amp04 rev. a C9C 10 90 100 0% 1mv 2s figure 7c. 10 hz low-pass filtered output power supply considerations in dual supply applications (for example 15 v) if the input is connected to a low resistance source less than 100 w , a large current may flow in the input leads if the positive supply is ap- plied before the negative supply during power-up. a similar condition may also result upon a loss of the negative supply. if these conditions could be present in you system, it is recom- mended that a series resistor up to 1 k w be added to the input leads to limit the input current. this condition can not occur in a single supply environment as losing the negative supply effectively removes any current return path. offset nulling in dual supply offset may be nulled by feeding a correcting voltage at the v ref pin (pin 5). however, it is important that the pin be driven with a low impedance source. any measurable resistance will degrade the amplifiers common-mode rejection performance as well as its gain accuracy. an op amp may be used to buffer the offset null circuit as in figure 8. 1 2 3 4 8 7 6 5 amp-04 v ref v+ r g + input ?v ?v +5v 50k 50k 100 w +5v ?v output +5v 5mv adj range * op-90 for low power op-113 for low drift * figure 8. offset adjust for dual supply applications offset nulling in single supply nulling the offset in single supply systems is difficult because the adjustment is made to try to attain zero volts. at zero volts out, the output is in saturation (to the negative rail) and the out- put voltage is indistinguishable from the normal offset error. consequently the offset nulling circuit in figure 9 must be used with caution. first, the potentiometer should be adjusted to cause the output to swing in the positive direction; then adjust it in the reverse direction, causing the output to swing toward ground, until the output just stops changing. at that point the output is at the saturation limit. 1 2 3 4 8 7 6 5 amp-04 r g input 50k 100 w +5v output +5v op-113 figure 9. offset adjust for single supply applications alternative nulling method an alternative null correction technique is to inject an off- set current into the summing node of the output amplifier as in figure 10. this method does not require an external op amp. however the drawback is that the amplifier will move off its null as the input common-mode voltage changes. it is a less desirable nulling circuit than the previ- ous method. 2 3 8 1 6 5 in(? in(+) input buffers r gain 100k ref 100k v out 11k 11k v+ v figure 10. current injection offsetting is not recommended
amp04 rev. a C10C application circuits low power precision single supply rtd amplifier figure 11 shows a linearized rtd amplifier that is powered off a single +5 volt supply. however, the circuit will work up to 36 volts without modification. the rtd is excited by a 100 m a constant current that is regulated by amplifier a (op295). the 0.202 volts reference voltage used to generate the constant cur- rent is divided down from the 2.500 volt reference. the amp04 amplifies the bridge output to a 10 mv/ c output coefficient. 100 w 7 1 6 5 4 2 3 8 +5v amp-04 8 7 4 5 6 +5v 50k r7 121k 1/2 op-295 1/2 op-295 a b ref-43 gnd out in 6 4 2 23 1 +5v c2 0.1 m f r1 26.7k r2 26.7k r4 100 w rtd 100 w r sense 1k r9 50 w r8 383 w c3 0.1 m f c1 0.47 m f r10 r6 11.5k 2.5v r5 1.02k 500 w 0.202v v out full-scale adj 0 ? 4.00v (0 c to 400 c) linearity adj. (@1/2 fs) notes: all resistors 0.5%, 25 ppm/ c all potentiometers 25 ppm/ c r3 balance figure 11. precision single supply rtd thermometer amplifier the rtd is linearized by feeding a portion of the signal back to the reference circuit, increasing the reference voltage as the tem- perature increases. when calibrated properly, the rtds non- linearity error will be canceled. to calibrate, either immerse the rtd into a zero-degree ice bath or substitute an exact 100 w resistor in place of the rtd. then adjust bridge balance potentiometer r3 for a 0 volt output. note that a 0 volt output is also the negative output swing limit of the amp04 powered with a single supply. there- fore, be sure to adjust r3 to first cause the output to swing positive and then back off until the output just stop swinging negatively. next, set the linearity adj. potentiometer to the mid- range. substitute an exact 247.04 w resistor (equivalent to 400 c temperature) in place of the rtd. adjust the full-scale potentiometer for a 4.000 volts output. finally substitute a 175.84 w resistor (equivalent to 200 c temperature), and adjust the linearity adj potentiometer for a 2.000 volts at the output. repeat the full-scale and the half-scale adjustments as needed. when properly calibrated, the circuit achieves better than 0.5 c accuracy within a temperature measurement range from 0 c to 400 c. precision 4-20 ma loop transmitter with noninteractive trim figure 12 shows a full bridge strain gage transducer amplifier circuit that is powered off the 4-20 ma current loop. the amp04 amplifies the bridge signal differentially and is con- verted to a current by the output amplifier. the total quiescent current drawn by the circuit, which includes the bridge, the am- plifiers, and the resistor biasing, is only a fraction of the 4 ma null current that flows through the current-sense resistor r sense . the voltage across r sense feeds back to the op90s in- put, whose common-mode is fixed at the current summing reference voltage, thus regulating the output current. with no bridge signal, the 4 ma null is simply set up by the 50 k w null potentiometer plus the 976 k w resistors that in- ject an offset that forces an 80 mv drop across r sense . at a 50 mv full-scale bridge voltage, the amp04 amplifies the voltage-to-current converter for a full-scale of 20 ma at the out- put. since the op90s input operates at a constant 0 volt common-mode voltage, the null and the span adjustments do figure 12. precision 4-20 ma loop transmitter features noninteractive trims
amp04 rev. a C11C not interact with one another. calibration is simple and easy with the null adjusted first, followed by span adjust. the entire circuit can be remotely placed, and powered from the 4-20 ma 2-wire loop. 4-20 ma loop receiver at the receiving end of a 4-20 ma loop, the amp04 makes a convenient differential receiver to convert the current back to a usable voltage (figure 13). the 4-20 ma signal current passes through a 100 w sense resistor. the voltage drop is differentially amplified by the amp04. the 4 ma offset is removed by the offset correction circuit. 7 1 6 5 4 2 3 8 amp-04 6 100k 0.15 m f 4?0ma trans- mitter power supply + 2 3 + 100 w 1% 1k 1k wire re- sistance in4002 ?.400v op-177 ad589 10k 27k ?5v +15v v out 0?.6v fs ?5v 4?0ma 4?0ma + figure 13. 4-to-20 ma line receiver low power, pulsed load-cell amplifier figure 14 shows a 350 w load cell that is pulsed with a low duty cycle to conserve power. the op295s rail-to-rail output capa- bility allows a maximum voltage of 10 volts to be applied to the bridge. the bridge voltage is selectively pulsed on when a mea- surement is made. a negative-going pulse lasting 200 ms should be applied to the measure input. the long pulse width is necessary to allow ample settling time for the long time constant of the low-pass filter around the amp04. a much faster settling time can be achieved by omitting the filter capacitor. 7 1 6 5 4 2 3 8 amp-04 0.22 m f +12v 1/2 op-295 ref-01 gnd out in +12v 330 w 1k 10k 10v 50k 2n3904 v out 1n4148 350 w measure figure 14. pulsed load cell bridge amplifier single sup ply programmable gain i nstrumentation amplifier combining with the single supply adg221 quad analog switch, the amp04 makes a useful programmable gain amplifier that can handle input and output signals at zero volts. figure 15 shows the implementation. a logic low input to any of the gain control ports will cause the gain to change by shorting a gain- set resistor across amp04s pins 1 and 8. trimming is required at higher gains to improve accuracy because the switch on- resistance becomes a more significant part of the gain-set resistance. the gain of 500 setting has two switches connected in parallel to reduce the switch resistance. 1 2 3 4 8 7 6 5 amp-04 v ref v+ + input v out +5v to +30v r g r g 0.1 m f 0.22 m f 100k 10.9k 3 14 715 w 200 w 200 w 6 11 4 5 adg221 +5v to +30v 13 10 9 7 8 15 16 2 1 12 + 10 m f 0.1 m f gain of 500 wr gain of 100 gain of 10 gain control figure 15. single supply programmable gain instrumen- tation amplifier the switch on resistance is lower if the supply voltage is 12 volts or higher. additionally the overall amplifiers tempera- ture coefficient also improves with higher supply voltage.
amp04 rev. a C12C 120 0 200 60 20 ?60 40 ?00 100 80 160 80 40 0 120 ?0 ?0 ?20 number of units input offset voltage ? m v based on 300 units 3 runs t a = +25 c v s = +5v v cm = 2.5v figure 16. input offset (v ios ) distribution @ +5 v 120 0 2.50 60 20 0.25 40 0 100 80 2.25 1.75 1.50 1.25 2.00 1.00 0.75 0.50 number of units tcv ios ? m v/ c 300 units v s = +5v v cm = 2.5v figure 18. input offset drift (tcv ios ) distribution @ +5 v 120 0 2.0 60 20 ?.6 40 ?.0 100 80 1.6 0.8 0.4 0 1.2 ?.4 ?.8 ?.2 number of units output offset ?mv based on 300 units 3 runs t a = +25 c v s = +5v v cm = 2.5v figure 20. output offset (v oos ) distribution @ +5 v 120 0 0.5 60 20 ?.4 40 ?.5 100 80 0.4 0.2 0.1 0 0.3 ?.1 ?.2 ?.3 number of units input offset voltage ?mv based on 300 units 3 runs t a = +25 c v s = 15v v cm = 0v figure 17. input offset (v ios ) distribution @ 15 v 120 0 2.50 60 20 0.25 40 0 100 80 2.25 1.75 1.50 1.25 2.00 1.00 0.75 0.50 number of units 300 units v s = 15v v cm = 0v tcv ios ? m v/ c figure 19. input offset drift (tcv ios ) distribution @ 15 v 120 0 5 60 20 ? 40 ? 100 80 4 2 1 03 ? ? ? number of units output offset ?mv based on 300 units 3 runs t a = +25 c v s = 15v v cm = 0v figure 21. output offset (v oos ) distribution @ 15 v
amp04 rev. a C13C 120 0 20 60 20 2 40 0 100 80 18 14 12 10 16 8 6 4 number of units tcv oos ? m v/ c 300 units v s = +5v v cm = 0v figure 22. output offset drift (tcv oos ) distribution @ +5 v temperature ? c 5.0 3.8 100 4.4 4.0 ?5 4.2 ?0 4.8 4.6 75 50 25 0 r l = 100k v s = +5v output voltage swing ?volts r l = 10k r l = 2k figure 24. output voltage swing vs. temperature @ +5 v temperature ? c 40 0 100 10 5 ?5 ?0 20 15 25 30 35 75 50 25 0 v s = +5v, v cm = 2.5v v s = 15v, v cm = 0v input bias current ?na v s = 15v v s = +5v figure 26. input bias current vs. temperature number of units tcv oos ? m v/ c 120 0 24 60 20 4 40 2 100 80 22 18 16 14 20 12 10 8 6 300 units v s = 15v v cm = 0v figure 23. output offset drift (tcv oos ) distribution @ 15 v temperature ? c 15.0 ?5.1 100 ?4.8 ?5.0 ?5 ?4.9 ?0 12.5 ?4.7 ?4.6 13.0 13.5 14.0 14.5 75 50 25 0 r l = 100k ?utput swing ?volts +output swing ?volts r l = 10k r l = 2k r l = 100k r l = 10k v s = +5v r l = 10k r l = 2k r l = 100k r l = 10k r l = 2k r l = 100k figure 25. output voltage swing vs. temperature @ +15 v temperature ? c input offset current ?na 8 0 ?0 100 6 2 ?5 4 50 75 25 0 v s = +5v, v cm = 2.5v v s = 15v , v cm = 0v v s = 15v v s = +5v figure 27. input offset current vs. temperature
amp04 rev. a C14C 50 30 ?0 1k 1m 100k 10k 100 40 10 20 ?0 0 frequency ?hz voltage gain ?db t a = +25 c v s = 15v g = 100 g = 10 g = 1 figure 28. closed-loop voltage gain vs. frequency 120 100 ?0 1 10 100k 10k 1k 100 80 60 40 20 0 t a = +25 c v s = 15v v cm = 2v p-p frequency ?hz common-mode rejection ?db g = 100 g = 10 g = 1 figure 30. common-mode rejection vs. frequency 140 120 0 10 100 1m 100k 10k 1k 100 80 60 40 20 t a = +25 c v s = 15v d v s = 1v frequency ?hz power supply rejection ?db g = 100 g = 10 g = 1 figure 32. positive power supply rejection vs. frequency 120 80 100 100k 10k 1k 10 100 40 60 0 20 frequency ?hz output impedance ? w t a = +25 c g = 1 v s = 15v v s = +5v figure 29. closed-loop output impedance vs. frequency common-mode rejection ?db 120 70 50 110 1k 100 100 60 80 90 110 t a = +25 c v s = 15v v cm = 2v p-p voltage gain ?g figure 31. common-mode rejection vs. voltage gain 140 120 0 10 100 1m 100k 10k 1k 100 80 60 40 20 t a = +25 c v s = 15v d v s = 1v frequency ?hz power supply rejection ?db g = 100 g = 10 g = 1 figure 33. ne gative power supply rejection vs. frequency
amp04 rev. a C15C 1k 100 1 110 1k 100 10 voltage gain ?g t a = +25 c v s = 15v ?= 100hz voltage noise ?nv/ hz figure 34. voltage noise density vs. gain 140 100 0 10 10k 1k 100 1 120 60 80 20 40 t a = +25 c v s = 15v g = 100 frequency ?hz voltage noise density ?nv/ hz figure 36. voltage noise density vs. frequency 1200 0 100 600 200 ?5 400 ?0 1000 800 75 50 25 0 temperature ? c supply current ? m a v s = +5v v s = 15v figure 38. supply current vs. temperature 1k 100 1 110 1k 100 10 voltage gain ?g t a = +25 c v s = 15v ?= 1khz voltage noise ?nv/ hz figure 35. voltage noise density vs. gain, f = 1 khz 10 90 100 0% 20mv 1s v s = 15v, gain = 1000, 0.1 to 10 hz bandpass figure 37. input noise voltage 16 8 0 100 100k 10k 1k 10 4 12 10 6 2 14 load resistance ? w t a = +25 c v s = 15v output voltage ?v figure 39. maximum output voltage vs. load resistance
amp04 rev. a C16C c1720C24C10/92 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) 0.160 (4.06) 0.115 (2.93) 0.130 (3.30) min 0.210 (5.33) max 0.015 (0.381) typ 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) 4 5 8 1 0.070 (1.77) 0.045 (1.15) 0.022 (0.558) 0.014 (0.356) 0.325 (8.25) 0.300 (7.62) 0 - 15 0.100 (2.54) bsc 0.015 (0.381) 0.008 (0.204) seating plane 0.195 (4.95) 0.115 (2.93) 8-lead cerdip (q-8) 0.005 (0.13) min 0.055 (1.4) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) max 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0 -15 0.015 (0.38) 0.008 (0.20) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 4 1 5 8 0.310 (7.87) 0.220 (5.59) 8-lead narrow-body so (s0-8)

▲Up To Search▲

Price & Availability of AMP04EP

	To Download AMP04EP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .